Crystal Growth
Monocrystalline silicon pulled by the Czochralski method, with SiC boule growth for the wide-bandgap roadmap.
- CZ pullers with automated diameter control
- Seed and tail-end engineering
- SiC boule growth program
RIFSOL · SILICON BOULE DIVISION
Silicon Boule Division
From crystal to 8-inch wafer.
Silicon and silicon-carbide substrates, grown, shaped and polished in-house — stage one of the RifSol value chain.
Czochralski growth8-inch Si8-inch SiCInline wafer QC
Overview
Stage one of a fully integrated platform
The Silicon Boule division is where every RifSol product begins: as a single-crystal ingot. Using Czochralski crystal growth, monocrystalline silicon is pulled, dimensioned and inspected before it ever reaches a saw. The same discipline extends to silicon carbide, whose extreme hardness and wide bandgap make it the substrate of choice for the next generation of power electronics.
Wafering is a precision chain of its own. Ingots are squared, sliced into 8-inch wafers, ground and lapped to remove saw damage, then finished with chemical-mechanical polishing (CMP) to reach the flatness and mirror finish that frontend lithography demands. Every step is paired with inline metrology so that geometry, surface quality and crystallographic properties are known wafer by wafer — not lot by lot.
Because substrates feed the RifSol frontend fab directly, the division operates under a phased deployment plan that grows capacity in step with downstream demand. Vertical control of the wafer line shortens feedback loops: a crystal-growth parameter, a polishing recipe or a cleaning step can be traced all the way to device yield, something separated merchant suppliers can rarely offer.
8-inch
Wafer diameter
Si + SiC
Two material platforms
100%
Inline wafer metrology
Stage 1
Of the 5-stage value chain
Capabilities
What Silicon Boule delivers
Ingot & Wafering
Squaring, slicing and edge shaping that turn boules into prime 8-inch wafers with minimal kerf loss.
- Multi-wire slicing
- Ingot squaring and orientation
- Edge rounding and Beilby-layer control
Grinding, Lapping & CMP
Damage removal followed by chemical-mechanical polishing to deliver epitaxy-ready surface finish.
- Wafer grinding and lapping
- CMP with slurry management
- Roughness down to mirror finish
Metrology & Wafer QC
Full-surface inspection for geometry, particles and crystal perfection before any wafer is released.
- TTV, bow and warp measurement
- Resistivity and lifetime checks
- Particle and defect scanning
Cleanroom Handling & Packaging
Wafer cassettes sealed and staged in cleanroom conditions, ready for direct transfer to the fab.
- ISO-class handling and packing
- Cassette and single-wafer shipping formats
- Traceability per wafer
Phased Capacity Deployment
Capacity for silicon and SiC wafers is added in phases, matched to the ramp of the frontend fab.
- Si 8-inch line first
- SiC line phasing in
- Supply continuity for RifSol products
Wafer specifications
Prime 8-inch wafers, specified.
Reference specifications for the two substrate platforms released to the frontend fab. Device-specific requirements are agreed with the IC Design Center per platform, and every wafer ships with full traceability.
8-inch Silicon Wafers
- Diameter: 200 mm (8-inch)
- Thickness: 725 μm, tight tolerance
- Crystal: Czochralski monocrystalline silicon
- Finish: CMP mirror surface, epitaxy-ready
- QC: geometry, resistivity and particles on every wafer
8-inch SiC Wafers
- Diameter: 200 mm (8-inch)
- Crystal: monocrystalline SiC boule, in-house growth program
- Finish: CMP polished for wide-bandgap device lines
- Deployment: phasing in behind the silicon line
- QC: full-surface geometry and defect screening
Wafer Release Flow
- Inline metrology before and after CMP
- Cleanroom handling: ISO-class cassetting and sealing
- Direct transfer path to the frontend fab
- Lot genealogy from crystal to cassette
How it works
The flow, step by step
- 01
Crystal Growth
A seed crystal draws a monocrystalline ingot from molten silicon (or SiC source material) under tightly controlled thermal gradients.
- 02
Squaring & Slicing
The ingot is orientation-checked, squared and multi-wire sliced into 8-inch wafers.
- 03
Grinding & Lapping
Saw damage is removed layer by layer, bringing each wafer to uniform thickness.
- 04
CMP Polishing
Chemical-mechanical polishing produces the defect-free mirror surface lithography requires.
- 05
Metrology & Inspection
Geometry, resistivity, particles and defects are measured on every wafer.
- 06
Cleanroom Packaging
Qualified wafers are cassetted, sealed and released to the frontend fab with full traceability.
Why it matters
A single crystal sets the ceiling for every chip.
Dislocations, oxygen content or resistivity striations created during growth cannot be fixed downstream — only detected. That is why crystal growth and wafer QC sit under the same roof as device engineering: the division does not just ship wafers, it ships wafers tuned to what the frontend fab will do with them.
Where it goes
Applications & industries
Power device substrates
Si and SiC wafers for MOSFET, IGBT and wide-bandgap device lines, including the RifSi frontend fab.
SiC for electrification
Silicon carbide substrates supporting high-efficiency EV powertrains, solar inverters and grid storage.
CMOS & mixed-signal starts
Prime 8-inch silicon for the 350–65 nm CMOS and BCD platforms processed next door.
Work with Silicon Boule.
From engineering programs to production partnership — the Silicon Boule team is one message away.