The last mile to a qualified chip.

Backend is where a proven die becomes a deliverable device. Wafers arriving from the frontend fab are die-sorted, then flow through die attach, interconnection and encapsulation before final electrical test. The division covers both standard package families and the power-specific builds — modules with multiple dies, baseplates and interconnects — that the RifSol power portfolio depends on.

Two interconnection technologies anchor the line. Wire bonding remains the workhorse for power and standard packages, with aluminum and copper systems tuned for current capability. Flip-chip packaging is deployed where inductance, footprint or thermal performance demand direct die-to-substrate connections. Both are supported by in-line inspection at every critical station.

Qualification is the real product of backend. Every device family passes burn-in and screening designed to precipitate infant mortality, plus reliability programs — temperature cycling, humidity, lifetime stress — aligned to the automotive and industrial quality systems of the platform. Failure analysis closes the loop: any field or test escape returns as a documented physical root cause, feeding both process and design.

Beyond wire bonding and flip-chip, the division operates an advanced-integration program built on three pillars. System-in-Package (SiP) combines several dies — logic, power, RF — with passives inside a single molded package. Chiplet integration places known-good dies side by side on a substrate or interposer and connects them with die-to-die interconnects, so a product is assembled from qualified building blocks instead of one monolithic die. And HBM rework covers the high-value end of the flow: controlled removal of a high-bandwidth-memory stack from its interposer or substrate, inspection of the underlying joints, and re-attachment of a known-good stack — recovering assemblies whose logic die is perfect but whose memory was not.